Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- RISC-V Conditional Moves (www.corsix.org)
- ARM is great, ARM is terrible, and so is RISC-V (changelog.complete.org)
- Adding a new instruction to RISC-V back end in LLVM (blog.gustavoleite.me)
- PA-RISC Performance and History (www.openpa.net)
- Linus Torvalds Lashes Out at RISC-V Big Endian Plans (www.phoronix.com)
- Condor Technology to Fly "Cuzco" RISC-V CPU into the Datacenter (www.nextplatform.com)
- ARM is great, ARM is terrible (and so is RISC-V) – The Changelog (changelog.complete.org)
- Meta reportedly buying RISC-V AI GPU firm Rivos (www.tomshardware.com)
- Meta Is Said to Acquire RISC-V Chips Startup Rivos to Push AI Effort (www.bloomberg.com)
- Chip designer SiFive aims to cram more RISC-V cores into AI chips (www.theregister.com)
- Tested on real silicon: Automating RISC-V Hardware-in-the-Loop (www.collabora.com)
- Xv6-Riscv 2025 Version (pdos.csail.mit.edu)
- Linus Torvalds Lashes Out at RISC-V Big Endian Plans (www.phoronix.com)
- Linus Torvalds Lashes Out at RISC-V Big Endian Plans (www.phoronix.com)
- RISC-V Conditional Moves (www.corsix.org)
- Xcena MX1 RISC-V Computational Memory in CXL 3.0 (www.servethehome.com)
- SiFive releases second generation of AI focused RISC-V IP (www.sifive.com)
- I used a RISC-V to make an analog tape drive [video] (www.youtube.com)
- RISC-V Conditional Moves (www.corsix.org)
- AI-Driven Software Porting to RISC-V (riscv.org)