Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- Senior Intel CPU architects splinter to develop RISC-V processors (www.tomshardware.com)
- LuaJIT PR: Add Support for RISC-V 64 (github.com)
- RISC-V CPU arrives on a tablet starting at $149 (www.tomshardware.com)
- PyPy gets a new RISC-V JIT back end (pypy.org)
- Tenstorrent's Blackhole chips boast 768 RISC-V cores and almost as many FLOPS (www.theregister.com)
- Box64 and RISC-V in 2024 (box86.org)
- $149 RISC-V Tablet Runs Ubuntu 24.04 (www.omgubuntu.co.uk)
- Using OneAPI and TornadoVM to Accelerate Java Programs on x86, ARM and RISC-V (jjfumero.github.io)
- Linux Up and Running on the Raspberry Pi RP2350's Hazard3 RISC-V Cores (www.hackster.io)
- SiFive shifts from RISC-V cores for AI chips to designing its own accelerator (www.theregister.com)
- Using RISC-V cores on the RP2350 MCU – blinking an LED to building Linux (www.cnx-software.com)
- $149 RISC-V Tablet Runs Ubuntu 24.04 – OMG Ubuntu (www.omgubuntu.co.uk)
- Hot Chips 24: XiangShan high perf RISC-V CPU (www.servethehome.com)
- Tenstorrent's Blackhole chips boast 768 RISC-V cores and almost as many FLOPS (www.theregister.com)
- Blinking LED to Building Linux Using RISC-V Cores on RPi Pico 2 and RP2350 MCU (www.cnx-software.com)
- Tenstorrent details its RISC-V packed Blackhole chips (www.theregister.com)
- XiangShan High-Performance RISC-V Processors at Hot Chips 2024 (www.servethehome.com)
- AheadComputing creates compelling RISC-V core IP (www.aheadcomputing.com)
- SWAR UTF-8 Validation with the hidden RISC-V gem xperm4 (camel-cdr.github.io)
- XiangShan High-Performance RISC-V Processors at Hot Chips 2024 (www.servethehome.com)
- Meta showcases RISC-V cores that will power recommendations (www.techradar.com)
- TamaGo Allows Executing Go Language Code Bare Metal on ARM/RISC-V SoCs (www.phoronix.com)
- TamaGo Allows Executing Go Language Code Bare Metal on ARM/RISC-V SoCs (www.phoronix.com)
- DeepComputing Announces the DC-ROMA RISC-V Pad II (deepcomputing.io)
- RISC OS (www.riscosopen.org)
- Eric Quinnell's critic on RISC-V, slidedeck (twitter.com)