Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- RISC-V RVA23 Profile: A major milestone (riscv.org)
- “Moonshots” Initiative to Secure the Future of RISC OS (www.riscosopen.org)
- Banana Pi BPI-RV2 RISC-V gateway board (docs.banana-pi.org)
- Long-term L1 execution layer proposal: replace the EVM with RISC-V (ethereum-magicians.org)
- Chinese project aims to run RISC-V code on AMD Zen processors (www.tomshardware.com)
- OrangePi RV2: The New Reference SBC for RISC-V Enthusiasts (boilingsteam.com)
- OrangePi RV2: The New Reference SBC for RISC-V Enthusiasts – Full Review (boilingsteam.com)
- China's push for chip independence continues with its first RISC-V server CPU (www.tomshardware.com)
- "Moonshots" Initiative to Secure the Future of RISC OS (www.riscosopen.org)
- Fedora 42 RISC-V Released – Builds for SiFive HiFive Premier P550 and Milk-V (www.phoronix.com)
- Banana Pi Teases BPI-CM6 Module Featuring SpacemiT K1 RISC-V Processor (linuxgizmos.com)
- Vitalik Buterin Proposes Replacing Ethereum's EVM with RISC-V (www.coindesk.com)
- China to publish policy to boost RISC-V chip use nationwide (www.reuters.com)
- Infineon announces first RISC-V microcontroller family for automotives (www.infineon.com)
- RISC-V vector extension overview (0x80.pl)
- Support for a 64-bit RISC-V Linux port of Rust to Tier-1 (riseproject.dev)
- DeepComputing – SpacemiT Muse Book RISC-V Laptop (store.deepcomputing.io)
- RISC-V with Linux 6.15 Adds Support for BFloat16 "BF16" Instructions (www.phoronix.com)