Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- RISC-V Vector Primer (github.com)
- Box64 Expands into RISC-V and LoongArch territory (boilingsteam.com)
- SpacemiT K3 RISC-V AI CPU launch event [video] (www.youtube.com)
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU (www.barchart.com)
- New SpacemiT K3 RISC-V Chip Beats Raspberry Pi 5 in Early Benchmarks (www.cnx-software.com)
- Binutils 2.46 Released – AMD, ARM, RISC-V, SFrame v3 (sourceware.org)
- Jupiter 2 – RVA23-compliant SBC features SpacemiT K3 octa-core RISC-V AI SoC (www.cnx-software.com)
- RISC-V Vector Primer (github.com)
- RISC-V User-Space Control Flow Integrity / Shadow Stack Appears Ready (www.phoronix.com)
- Visualizing the RISC-V Instruction Set (gist.github.com)
- Security Researchers Find Current RISC-V CPU Implementations Coming Up Short (www.phoronix.com)
- A nice little RISC-V ESP32-P4 board with USB, HDMI and Ethernet (www.cnx-software.com)
- DeepComputing Announced Early Access for the DC-ROMA RISC-V Mainboard III (store.deepcomputing.io)
- CentOS is coming to RISC-V soon if you have the kit (www.theregister.com)
- Show HN: Modeling "Dragon King" wildfire events with 5-mile frontier effects (gethazardsafe.com)
- Rise of the Triforce (dolphin-emu.org)
- Hard-braking events as indicators of road segment crash risk (research.google)