Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- Rocky Linux 10 Will Support RISC-V (rockylinux.org)
- Felix86: Run x86-64 programs on RISC-V Linux (felix86.com)
- Implementing a RISC-V Hypervisor (seiya.me)
- The RISC OS GUI (telcontar.net)
- RISC-V Turns 15 with Fast Global Adoption (www.eetimes.com)
- Felix86: Play x86-64 games on RISC-V (github.com)
- RVPC Adds Basic Interpreter to €1 Open Source RISC-V Computer (linuxgizmos.com)
- Initial CentOS Support for RISC-V (blog.centos.org)
- Mobile, Open Hardware, RISC-V System-on-Chip (SoC) Development Kit (www.crowdsupply.com)
- The Genius of RISC-V Microprocessors (2020) (erik-engheim.medium.com)
- Common Lisp disassembly through SBCL on RISC-V architecture (morphykuffour.github.io)
- High RISC, High Reward: RISC-V at 15 (riscv.org)
- High RISC, High Reward: RISC-V at 15 (riscv.org)
- Ethereum: Vitalik Buterin wants RISC-V for Ethereum smart contracts (www.tradingview.com)
- Show HN: Miralis – a RISC-V virtual firmware monitor (github.com)
- GCC 16 Lands Better Support for -march= Targeting on RISC-V (www.phoronix.com)
- Framework Laptop: RISC-V Mainboard II: DC-ROMA AI PC (store.deepcomputing.io)
- Full Steam Ahead with RISC-V and Fedora Linux 42 (fedoramagazine.org)
- Need Suggestions for Riscv CPU (github.com)
- The Orange Pi RV2 RISC-V SBC (taoofmac.com)
- A Comparison between WebAssembly and RISC-V (2020) (medium.com)
- Why ZKM Chose MIPS32r2 over RISC-V for ZkMIPS (www.zkm.io)