Hackernews posts about RISC
RISC is an acronym for Reduced Instruction Set Computing, referring to a computer architecture that simplifies instruction sets to improve processing efficiency and performance.
Related:
Arch Linux CISC
- RISC-V: They Should Have Known Better (dmitry.gr)
- RISC-V: They should have known better (dmitry.gr)
- Twenty Years of RISC OS Open (www.riscosopen.org)
- The Alpha 21264 CPU: NT's Greatest RISC (1998) (halfhill.com)
- Pushing the limits of RISC-V emulation (shuklaayu.sh)
- Comu – $6 RISC-V board that fits inside a USB port (www.cnx-software.com)
- RISC-V Extension Landscape (rpsene.github.io)
- Booting Fuchsia's Zircon on a Homebrew RISC-V SoC, on an Artix-7 FPGA (www.hdlfactory.com)
- Spectre on RISC-V Silicon (lukasgerlach.me)
- Humble Bundle: Embedded Firmware Books on ARM, RTOS, RISC-V and Linux (www.humblebundle.com)
- Pushing the limits of RISC-V emulation (shuklaayu.sh)
- NetBSD 11 lands with RISC-V support and fast VM boots (www.theregister.com)
- Spectre on RISC-V Silicon [pdf] (lukasgerlach.me)
- RISC-V: What Matters (thechipletter.substack.com)
- RISC-V: Public Review for the RVA23.1 and RVB23.1 Profiles (groups.google.com)
- RISC-V rave: WASM-based RISC-V emulator (writethat.blog)
- Running models on RISC-V with IREE (iree.dev)
- Semaglutide linked to lower predicted dementia risk (alz-journals.onlinelibrary.wiley.com)
- Nvidia's Risky Business (stratechery.com)
- Babies born under sugar rationing grew into adults with lower cancer risk (theconversation.com)
- Midlife Vascular Risk Burden and Dementia-Free Survival Years (www.neurology.org)