Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

Related: FPGA RISC-V Python

Verilog – Hardware register based language for standardization (en.wikipedia.org)

1 points by Lain-Pajama 26 days ago | discuss
Ask HN: What are some great ESP32 DIY pojects for Xmas gifts

2 points by TechDebtDevin 15 days ago | 2 comments
Senators Call for Crackdown on VeriSign Monopoly and Predatory Pricing of .com (www.wired.com)

8 points by impish9208 about 12 hours ago | discuss
Tiny GPU: A minimal GPU implementation in Verilog (github.com)

315 points by fgblanch 7 months ago | 73 comments
Verilog to Routing (verilogtorouting.org)

107 points by stefanpie about 1 year ago | 29 comments
Verilog Ethernet: Work-in-Progress 100BASE-TX PHY (github.com)

95 points by pabs3 over 1 year ago | 65 comments
Learning Verilog and FPGA (johanneshoff.com)

95 points by bajsejohannes almost 2 years ago | 29 comments
Verilog HDL and its ancestors and descendants (2020) [pdf] (dl.acm.org)

28 points by JoachimS 11 months ago | 7 comments
Show HN: Naja-Verilog – Structural Verilog Parser (github.com)

17 points by xtofalex over 1 year ago | 3 comments
Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)

15 points by matt_d 2 months ago | 2 comments
Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)

13 points by sathvikr 4 months ago | 7 comments
Package Manager for Verilog (github.com)

6 points by sathvikr 4 months ago | 7 comments
Show HN: I made an interview platform for hardware engineers in Verilog (bithacker.io)

5 points by bithacker23 almost 2 years ago | discuss
Verilog vs. VHDL: A Comprehensive Comparison (www.wevolver.com)

4 points by alexahn about 1 year ago | 1 comments
Verilog2factorio: Compile Verilog into Factorio Blueprints (github.com)

4 points by EvgeniyZh 7 months ago | discuss
Writing a 6502 in Verilog (www.youtube.com)

3 points by lagrange77 10 months ago | discuss
My Six Lines of Verilog Code Turing Complete BitBitJump Is Now Under the GPLv3 (gitlab.com)

3 points by pantantrant 10 months ago | discuss
Learn FPGAs, Verilog and VHDL (nandland.com)

3 points by teleforce over 1 year ago | discuss
Lattice-Boltzmann in Python, C, and Verilog (vanhunteradams.com)

3 points by vha3 over 1 year ago | discuss
OpenROAD: Open IC Design Sythesis from Verilog (github.com)

3 points by f_devd over 1 year ago | discuss
Variable-size Verilog floating point implementation (github.com)

2 points by douwedb 10 months ago | 1 comments
HDLBits: Getting Started with Verilog (hdlbits.01xz.net)

2 points by pera about 1 month ago | discuss
Pip Install for Verilog (github.com)

2 points by sathvikr 3 months ago | discuss
Verilog Programs Are Pure Expressions (uwplse.org)

2 points by matt_d 4 months ago | discuss
Python-Based DSL for Generating Verilog Model of Synchronous Digital Circuits (arxiv.org)

2 points by belter 5 months ago | discuss
Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)

2 points by coconutpalms 9 months ago | discuss
The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog (dl.acm.org)

2 points by matt_d about 1 year ago | discuss
A next generation Verilog-A compiler (github.com)

2 points by alex_hirner almost 2 years ago | discuss
VerilogBoy – GameBoy on FPGA (hackaday.io)

2 points by _Microft almost 2 years ago | discuss
Sussing Out SystemVerilog vs. Verilog (fpgacoding.com)

1 points by jnord 3 months ago | discuss
Setting Up Verible for Verilog with Neovim (danielmangum.com)

1 points by hasheddan about 1 year ago | discuss
Simulating DSP algorithms using Verilog (www.controlpaths.com)

1 points by hasheddan over 1 year ago | discuss
Show HN: Manta – A tool for FPGA Debugging and Rapid Prototyping (fischermoseley.github.io)

86 points by fischerm 9 months ago | 5 comments