Hackernews posts about Verilog
Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.
- Verizon outages reported across U.S. (www.firstcoastnews.com)
- Verizon Wireless Is Down (downdetector.com)
- FCC Helps Verizon Make It Harder for You to Switch Wireless Carriers (www.techdirt.com)
- Verizon Is Down (www.macrumors.com)
- Verizon is down, with many users seeing 'SOS' – here's everything we know (www.techradar.com)
- Verizon just had a big outage. Here's what we know (text.npr.org)
- Verizon starts issuing $20 credits after nationwide outage (www.bleepingcomputer.com)
- The Day the Cell Towers Died (www.wsj.com)
- Local AI apps worldwide 26 Dec 2025 (old.reddit.com)
- Tiny GPU: A minimal GPU implementation in Verilog (github.com)
- Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
- Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- Package Manager for Verilog (github.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
- Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
- Writing a 6502 in Verilog (www.youtube.com)
- Variable-size Verilog floating point implementation (github.com)
- Show HN: From Nandgame to Verilog to FPGA (github.com)
- Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
- Improving Verilog Four State Logic (cjdrake.substack.com)
- VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
- HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
- Pip Install for Verilog (github.com)
- Verilog Programs Are Pure Expressions (uwplse.org)
- Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
- Basic Cordic implementation in Rust and Verilog (github.com)
- ao486 port for MiSTer (486SX FPGA core in Verilog) (github.com)
- Formal Verification for Verilog Using Yosys (cheickdo.github.io)