Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator (github.com)
   119 points by gdevic 17 days ago | 42 comments
2. NovaGPU – An open-source GPU architecture written in Verilog (github.com)
   4 points by novastudios-hw 4 days ago | discuss
3. A permissively licensed Vita FPGA Architecture in only 380 lines of Verilog (github.com)
   2 points by VitaSetLLC 11 days ago | 1 comments
4. New PyXHDL Release (Python Frontend To VHDL And Verilog) (github.com)
   2 points by dadaz 26 days ago | discuss
5. Verilog: Back to the building blocks' building blocks (www.cs.cornell.edu)
   1 points by fanf2 5 days ago | discuss
6. Ask HN: High-level hardware description language?
   2 points by nyeah 17 days ago | discuss
7. Verisign to delete .name 3LDs and email addresses (domainincite.com)
   5 points by zacwest 19 days ago | 1 comments
8. Veryl Simulator: Performance Comparison with Verilator (veryl-lang.org)
   3 points by dalance 6 days ago | discuss
9. Vericoding: The End of "Trust Me Bro, The AI Wrote It" (blog.icme.io)
   3 points by _doctor_love 8 days ago | discuss
10. AT&T, T-Mobile, and Verizon to eliminate coverage dead zones (www.theverge.com)
    1 points by mchusma 18 days ago | 1 comments
11. VeilGate- Deception Reverse Proxy
    1 points by C0oki3s 13 days ago | discuss
12. Complete sequence of Orthohantavirus andesense virus: Swiss resident 2026 (virological.org)
    2 points by bschne 21 days ago | discuss
13. Show HN: An update to our long-turn FreeCiv experience (freeciv.andrewmcgrath.info)
    5 points by verelo 5 days ago | discuss
14. Show HN: Find YC startups relevant to you (platoseed.com)
    3 points by nerdlogic about 20 hours ago | discuss
15. A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (github.com)
    154 points by signa11 2 months ago | 22 comments
16. OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020) (github.com)
    87 points by peter_d_sherman 12 months ago | 9 comments
17. Vectorization of Verilog Designs and its Effects on Verification and Synthesis (arxiv.org)
    35 points by matt_d 2 months ago | 6 comments
18. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
    15 points by matt_d over 1 year ago | 2 comments
19. Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
    13 points by sathvikr almost 2 years ago | 7 comments
20. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti over 1 year ago | 1 comments
21. Inline-Verilog: Execute Verilog circuits from Haskell (mazzo.li)
    10 points by nh2 12 months ago | discuss
22. From Pal to Verilog: Writing the A4092 Logic from Scratch (amiga.technology)
    7 points by freediver about 2 months ago | discuss
23. Package Manager for Verilog (github.com)
    6 points by sathvikr almost 2 years ago | 7 comments
24. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule over 1 year ago | discuss
25. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca about 1 year ago | 4 comments
26. Verijit – Up to 100x faster Verilog simulation [video] (www.youtube.com)
    4 points by can_lehmann about 1 month ago | discuss
27. I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
    3 points by JamesEvery about 1 year ago | 1 comments
28. Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
    3 points by matt_d 3 months ago | discuss
29. CVDP: LLM Benchmark for Verilog RTL Design and Verification (arxiv.org)
    3 points by matt_d 11 months ago | discuss
30. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake over 1 year ago | discuss
31. Building an Open-Source Verilog Simulator with AI (normalcomputing.com)
    2 points by krupan 3 months ago | 1 comments
32. HBC (2016): Hand-Written Verilog for Offloading Column-Oriented DBs to the NIC (note.com)
    2 points by victrious 3 months ago | 1 comments
33. PyXHDL – Python Front End for VHDL and Verilog (github.com)
    2 points by dadaz about 2 months ago | discuss
34. Show HN: From Nandgame to Verilog to FPGA (github.com)
    2 points by xocp about 1 year ago | discuss
35. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd about 1 year ago | discuss
36. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa over 1 year ago | discuss
37. VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
    2 points by teleforce over 1 year ago | discuss
38. Ask HN: Are there open source flow graph based Verilog generators?
    2 points by polalavik over 1 year ago | discuss
39. HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
    2 points by pera over 1 year ago | discuss
40. Pip Install for Verilog (github.com)
    2 points by sathvikr almost 2 years ago | discuss
41. Verilog Programs Are Pure Expressions (uwplse.org)
    2 points by matt_d almost 2 years ago | discuss
42. Python-Based DSL for Generating Verilog Model of Synchronous Digital Circuits (arxiv.org)
    2 points by belter almost 2 years ago | discuss
43. Room: Verilog for Read-Once-Only Memory (Quantum-Inspired Security Primitive) (github.com)
    1 points by networkcrypt 9 months ago | 1 comments
44. Basic Cordic implementation in Rust and Verilog (github.com)
    1 points by xphos about 1 year ago | 1 comments