Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. Show HN: FPGA-SIM – interactive virtual boards to help teach Verilog (github.com)
   2 points by theharmonic 8 days ago | 1 comments
2. Show HN: FPGA design acceleration – idiomatic Python to synthesizable Verilog (holoso.digital)
   2 points by spym_ 19 days ago | discuss
3. Verizon is about to break our Gizmo watches (www.jefftk.com)
   154 points by jefftk 12 days ago | 120 comments
4. A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (github.com)
   154 points by signa11 4 months ago | 22 comments
5. Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator (github.com)
   119 points by gdevic 2 months ago | 42 comments
6. OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020) (github.com)
   87 points by peter_d_sherman about 1 year ago | 9 comments
7. Vectorization of Verilog Designs and its Effects on Verification and Synthesis (arxiv.org)
   35 points by matt_d 4 months ago | 6 comments
8. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
   15 points by matt_d almost 2 years ago | 2 comments
9. Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
   13 points by sathvikr almost 2 years ago | 7 comments
10. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti over 1 year ago | 1 comments
11. Inline-Verilog: Execute Verilog circuits from Haskell (mazzo.li)
    10 points by nh2 about 1 year ago | discuss
12. From Pal to Verilog: Writing the A4092 Logic from Scratch (amiga.technology)
    7 points by freediver 3 months ago | discuss
13. Package Manager for Verilog (github.com)
    6 points by sathvikr almost 2 years ago | 7 comments
14. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule over 1 year ago | discuss
15. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca over 1 year ago | 4 comments
16. Show HN: AutoGPU – AI designs a real 7nm GPU, from Verilog to GDSII (github.com)
    4 points by npip99 about 1 month ago | discuss
17. NovaGPU – An open-source GPU architecture written in Verilog (github.com)
    4 points by novastudios-hw about 2 months ago | discuss
18. Verijit – Up to 100x faster Verilog simulation [video] (www.youtube.com)
    4 points by can_lehmann 3 months ago | discuss
19. I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
    3 points by JamesEvery about 1 year ago | 1 comments
20. Giulioz: MMO-CHIP: From Microscope to Verilog in an hour [video] (www.youtube.com)
    3 points by rasz about 1 month ago | discuss
21. Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
    3 points by matt_d 5 months ago | discuss
22. CVDP: LLM Benchmark for Verilog RTL Design and Verification (arxiv.org)
    3 points by matt_d about 1 year ago | discuss
23. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake over 1 year ago | discuss
24. A permissively licensed Vita FPGA Architecture in only 380 lines of Verilog (github.com)
    2 points by VitaSetLLC about 2 months ago | 1 comments
25. Building an Open-Source Verilog Simulator with AI (normalcomputing.com)
    2 points by krupan 4 months ago | 1 comments
26. HBC (2016): Hand-Written Verilog for Offloading Column-Oriented DBs to the NIC (note.com)
    2 points by victrious 5 months ago | 1 comments
27. Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
    2 points by hasheddan about 1 month ago | discuss
28. New PyXHDL Release (Python Frontend To VHDL And Verilog) (github.com)
    2 points by dadaz 2 months ago | discuss
29. PyXHDL – Python Front End for VHDL and Verilog (github.com)
    2 points by dadaz 3 months ago | discuss
30. Show HN: From Nandgame to Verilog to FPGA (github.com)
    2 points by xocp about 1 year ago | discuss
31. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd over 1 year ago | discuss
32. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa over 1 year ago | discuss
33. VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
    2 points by teleforce over 1 year ago | discuss