Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. Show HN: SHDL – A minimal hardware description language built from logic gates (github.com)
   48 points by rafa_rrayes 14 days ago | 21 comments
2. Show HN: SHDL – A minimal hardware description language built from logic gates (github.com)
   2 points by rafa_rrayes 16 days ago | 2 comments
3. AT&T, Verizon blocking release of Salt Typhoon security assessment reports (www.reuters.com)
   300 points by redman25 2 days ago | 81 comments
4. Verizon starts requiring 365 days of paid service before it will unlock phones (arstechnica.com)
   100 points by voxadam 21 days ago | 125 comments
5. Verizon to stop automatic unlocking of phones as FCC ends 60-day unlock rule (arstechnica.com)
   20 points by DefineOutside 29 days ago | 2 comments
6. Verizon to stop automatic unlocking of phones as FCC ends 60-day unlock rule (arstechnica.com)
   15 points by cdrnsf 29 days ago | discuss
7. Verizon Is Down (www.macrumors.com)
   7 points by vapemaster 27 days ago | 4 comments
8. Verizon is down, with many users seeing 'SOS' – here's everything we know (www.techradar.com)
   7 points by bluedino 28 days ago | 1 comments
9. AT&T, Verizon blocking release of Salt Typhoon security assessment reports (www.reuters.com)
   4 points by toomuchtodo 7 days ago | 1 comments
10. Verizon's Hourslong Wireless Outage Tied to Software Update (www.wsj.com)
    4 points by jbredeche 27 days ago | 1 comments
11. Verizon completed its $20B acquisition of Frontier Communications (www.verizon.com)
    4 points by samgutentag 20 days ago | discuss
12. Virology Lectures 2025 [video] (www.youtube.com)
    4 points by shpx 21 days ago | discuss
13. FCC revises Verizon phone unlocking rules after significant fraud issues (www.reuters.com)
    4 points by petethomas 29 days ago | discuss
14. Verizon carriers start switching to 365day device unlock policy, up from 60 days (9to5google.com)
    3 points by thunderbong 21 days ago | 1 comments
15. Verizon Outage (apnews.com)
    3 points by zephyreon 28 days ago | 1 comments
16. A benchmark for LLM vericoding: formally verified program synthesis (arxiv.org)
    2 points by cpeterso 27 days ago | discuss
17. Show HN: I created a Mars colony RPG based on Kim Stanley Robinson’s Mars books (underhillgame.com)
    304 points by ariaalam 3 days ago | 110 comments
18. Tiny GPU: A minimal GPU implementation in Verilog (github.com)
    315 points by fgblanch almost 2 years ago | 73 comments
19. OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020) (github.com)
    87 points by peter_d_sherman 8 months ago | 9 comments
20. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
    15 points by matt_d over 1 year ago | 2 comments
21. Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
    13 points by sathvikr over 1 year ago | 7 comments
22. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti about 1 year ago | 1 comments
23. Inline-Verilog: Execute Verilog circuits from Haskell (mazzo.li)
    10 points by nh2 8 months ago | discuss
24. Package Manager for Verilog (github.com)
    6 points by sathvikr over 1 year ago | 7 comments
25. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule 12 months ago | discuss
26. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca 11 months ago | 4 comments
27. Verilog2factorio: Compile Verilog into Factorio Blueprints (github.com)
    4 points by EvgeniyZh almost 2 years ago | discuss
28. I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
    3 points by JamesEvery 9 months ago | 1 comments
29. CVDP: LLM Benchmark for Verilog RTL Design and Verification (arxiv.org)
    3 points by matt_d 8 months ago | discuss
30. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake about 1 year ago | discuss
31. Show HN: From Nandgame to Verilog to FPGA (github.com)
    2 points by xocp 9 months ago | discuss
32. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd 11 months ago | discuss
33. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa about 1 year ago | discuss
34. VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
    2 points by teleforce about 1 year ago | discuss
35. Ask HN: Are there open source flow graph based Verilog generators?
    2 points by polalavik about 1 year ago | discuss
36. HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
    2 points by pera over 1 year ago | discuss
37. Pip Install for Verilog (github.com)
    2 points by sathvikr over 1 year ago | discuss
38. Verilog Programs Are Pure Expressions (uwplse.org)
    2 points by matt_d over 1 year ago | discuss
39. Python-Based DSL for Generating Verilog Model of Synchronous Digital Circuits (arxiv.org)
    2 points by belter over 1 year ago | discuss
40. Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
    2 points by coconutpalms almost 2 years ago | discuss
41. Room: Verilog for Read-Once-Only Memory (Quantum-Inspired Security Primitive) (github.com)
    1 points by networkcrypt 5 months ago | 1 comments
42. Basic Cordic implementation in Rust and Verilog (github.com)
    1 points by xphos 11 months ago | 1 comments
43. ao486 port for MiSTer (486SX FPGA core in Verilog) (github.com)
    1 points by peter_d_sherman 4 months ago | discuss
44. Tiny-NN: A Toy Neural Network Accelerator in System Verilog (github.com)
    1 points by hasheddan 11 months ago | discuss
45. Formal Verification for Verilog Using Yosys (cheickdo.github.io)
    1 points by yatrios 12 months ago | discuss
46. Verilog – Hardware register based language for standardization (en.wikipedia.org)
    1 points by Lain-Pajama over 1 year ago | discuss
47. Sussing Out SystemVerilog vs. Verilog (fpgacoding.com)
    1 points by jnord over 1 year ago | discuss