Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. Verizon to cut about 15,000 jobs (www.reuters.com)
   6 points by lambersley 19 days ago | 4 comments
2. Verizon to Cut About 15,000 Jobs (www.wsj.com)
   3 points by LostMyLogin 19 days ago | discuss
3. T-Mobile Brings Free 911 Emergency Texting to AT&T and Verizon Customers (www.theverge.com)
   3 points by m463 27 days ago | discuss
4. Are Verizon's Layoffs a Warning for White-Collar Jobs in the AI Era? (cceonlinenews.com)
   1 points by mooreds 14 days ago | discuss
5. Show HN: Bringing stacked diff workflow to Perforce (github.com)
   1 points by kai2006 8 days ago | discuss
6. Kohler Can Access Data from Toilet Camera It Describes as "End-to-End Encrypted" (varlogsimon.leaflet.pub)
   3 points by BCM43 about 1 hour ago | 2 comments
7. Enveloped vs. Non-Enveloped Virus(2022) (virologyresearchservices.com)
   2 points by rolph 5 days ago | discuss
8. Tiny GPU: A minimal GPU implementation in Verilog (github.com)
   315 points by fgblanch over 1 year ago | 73 comments
9. OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020) (github.com)
   87 points by peter_d_sherman 6 months ago | 9 comments
10. Verilog HDL and its ancestors and descendants (2020) [pdf] (dl.acm.org)
    28 points by JoachimS almost 2 years ago | 7 comments
11. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
    15 points by matt_d about 1 year ago | 2 comments
12. Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
    13 points by sathvikr over 1 year ago | 7 comments
13. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti 10 months ago | 1 comments
14. Inline-Verilog: Execute Verilog circuits from Haskell (mazzo.li)
    10 points by nh2 6 months ago | discuss
15. Package Manager for Verilog (github.com)
    6 points by sathvikr over 1 year ago | 7 comments
16. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule 9 months ago | discuss
17. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca 9 months ago | 4 comments
18. Verilog2factorio: Compile Verilog into Factorio Blueprints (github.com)
    4 points by EvgeniyZh over 1 year ago | discuss
19. I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
    3 points by JamesEvery 7 months ago | 1 comments
20. CVDP: LLM Benchmark for Verilog RTL Design and Verification (arxiv.org)
    3 points by matt_d 5 months ago | discuss
21. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake 12 months ago | discuss
22. Writing a 6502 in Verilog (www.youtube.com)
    3 points by lagrange77 almost 2 years ago | discuss
23. Variable-size Verilog floating point implementation (github.com)
    2 points by douwedb almost 2 years ago | 1 comments
24. Show HN: From Nandgame to Verilog to FPGA (github.com)
    2 points by xocp 7 months ago | discuss
25. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd 9 months ago | discuss
26. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa 11 months ago | discuss
27. VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
    2 points by teleforce 11 months ago | discuss
28. Ask HN: Are there open source flow graph based Verilog generators?
    2 points by polalavik 12 months ago | discuss
29. HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
    2 points by pera about 1 year ago | discuss
30. Pip Install for Verilog (github.com)
    2 points by sathvikr over 1 year ago | discuss
31. Verilog Programs Are Pure Expressions (uwplse.org)
    2 points by matt_d over 1 year ago | discuss
32. Python-Based DSL for Generating Verilog Model of Synchronous Digital Circuits (arxiv.org)
    2 points by belter over 1 year ago | discuss
33. Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
    2 points by coconutpalms almost 2 years ago | discuss
34. Room: Verilog for Read-Once-Only Memory (Quantum-Inspired Security Primitive) (github.com)
    1 points by networkcrypt 3 months ago | 1 comments
35. Basic Cordic implementation in Rust and Verilog (github.com)
    1 points by xphos 9 months ago | 1 comments
36. ao486 port for MiSTer (486SX FPGA core in Verilog) (github.com)
    1 points by peter_d_sherman about 2 months ago | discuss
37. Tiny-NN: A Toy Neural Network Accelerator in System Verilog (github.com)
    1 points by hasheddan 9 months ago | discuss