Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014) (github.com)
   73 points by csmantle 29 days ago | 14 comments
2. TPU: Tensor-Processing-Unit – Open-Source Verilog TPU (github.com)
   3 points by peter_d_sherman 21 days ago | discuss
3. Verifrog – a Verilog/SystemVerilog testing framework an AI agent can drive (github.com)
   2 points by bryancostanich 19 days ago | discuss
4. Tiny-GPU – A minimal open-source GPU design in Verilog to learn how GPUs work (github.com)
   2 points by peter_d_sherman 21 days ago | discuss
5. Show HN: Convex clients in 100 programming languages (github.com)
   2 points by mikeyseee 12 days ago | discuss
6. Von Neumann's 1927 Trilogy on the Foundations of Quantum Mechanics (arxiv.org)
   3 points by throwaway81523 3 days ago | discuss
7. Very Perilous: A sword wounds compendium by the surgeon Ravaton (hemamisfits.com)
   2 points by bushwart about 3 hours ago | discuss
8. A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (github.com)
   154 points by signa11 5 months ago | 22 comments
9. Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator (github.com)
   119 points by gdevic 4 months ago | 42 comments
10. OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020) (github.com)
    87 points by peter_d_sherman about 1 year ago | 9 comments
11. Vectorization of Verilog Designs and its Effects on Verification and Synthesis (arxiv.org)
    35 points by matt_d 5 months ago | 6 comments
12. Show HN: Write, simulate and synthesize VHDL/Verilog in the browser (risingedge.pro)
    19 points by wozniakpawel about 1 month ago | 4 comments
13. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
    15 points by matt_d almost 2 years ago | 2 comments
14. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti over 1 year ago | 1 comments
15. Inline-Verilog: Execute Verilog circuits from Haskell (mazzo.li)
    10 points by nh2 about 1 year ago | discuss
16. From Pal to Verilog: Writing the A4092 Logic from Scratch (amiga.technology)
    7 points by freediver 5 months ago | discuss
17. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule over 1 year ago | discuss
18. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca over 1 year ago | 4 comments
19. Show HN: AutoGPU – AI designs a real 7nm GPU, from Verilog to GDSII (github.com)
    4 points by npip99 3 months ago | discuss
20. NovaGPU – An open-source GPU architecture written in Verilog (github.com)
    4 points by novastudios-hw 3 months ago | discuss
21. Verijit – Up to 100x faster Verilog simulation [video] (www.youtube.com)
    4 points by can_lehmann 4 months ago | discuss
22. I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
    3 points by JamesEvery over 1 year ago | 1 comments
23. Giulioz: MMO-CHIP: From Microscope to Verilog in an hour [video] (www.youtube.com)
    3 points by rasz 3 months ago | discuss
24. Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
    3 points by matt_d 6 months ago | discuss
25. CVDP: LLM Benchmark for Verilog RTL Design and Verification (arxiv.org)
    3 points by matt_d about 1 year ago | discuss
26. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake over 1 year ago | discuss
27. Show HN: FPGA-SIM – interactive virtual boards to help teach Verilog (github.com)
    2 points by theharmonic about 2 months ago | 1 comments
28. A permissively licensed Vita FPGA Architecture in only 380 lines of Verilog (github.com)
    2 points by VitaSetLLC 3 months ago | 1 comments
29. Building an Open-Source Verilog Simulator with AI (normalcomputing.com)
    2 points by krupan 6 months ago | 1 comments
30. HBC (2016): Hand-Written Verilog for Offloading Column-Oriented DBs to the NIC (note.com)
    2 points by victrious 6 months ago | 1 comments
31. Show HN: FPGA design acceleration – idiomatic Python to synthesizable Verilog (holoso.digital)
    2 points by spym_ 2 months ago | discuss
32. Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
    2 points by hasheddan 3 months ago | discuss
33. New PyXHDL Release (Python Frontend To VHDL And Verilog) (github.com)
    2 points by dadaz 4 months ago | discuss
34. PyXHDL – Python Front End for VHDL and Verilog (github.com)
    2 points by dadaz 5 months ago | discuss
35. Show HN: From Nandgame to Verilog to FPGA (github.com)
    2 points by xocp over 1 year ago | discuss
36. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd over 1 year ago | discuss
37. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa over 1 year ago | discuss