Hackernews posts about Verilog
Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.
- Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)
- Moore and Mealy Model in System Verilog (2025) (medium.com)
- Verizon imposes new roadblock on users trying to unlock paid-off phones (arstechnica.com)
- Tiny GPU: A minimal GPU implementation in Verilog (github.com)
- Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
- Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- Package Manager for Verilog (github.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
- Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
- Show HN: From Nandgame to Verilog to FPGA (github.com)
- Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
- Improving Verilog Four State Logic (cjdrake.substack.com)
- VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
- HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
- Pip Install for Verilog (github.com)
- Verilog Programs Are Pure Expressions (uwplse.org)
- Basic Cordic implementation in Rust and Verilog (github.com)
- ao486 port for MiSTer (486SX FPGA core in Verilog) (github.com)
- Formal Verification for Verilog Using Yosys (cheickdo.github.io)
- Verilog – Hardware register based language for standardization (en.wikipedia.org)
- Sussing Out SystemVerilog vs. Verilog (fpgacoding.com)
- Less Slow C++ (github.com)