Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

RSS feed for Verilog

Related:FPGA RISC-V Python

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newVeriLoop E2 Release: 27B Post-Trained Model and Full GGUF BF16 to IQ1_Mdiscuss.huggingface.co
▲ 1simonpure 19d 💬 1
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newShow HN: An Email-to-iMessage Gateway
▲ 2ajaygoel 12h 💬 1
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new1776 or 2026, Spot the Differenceetc.usf.edu
▲ 2trilogic 19h discuss
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newA Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)github.com
▲ 154signa11 202d 💬 22
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newShow HN: A nibble-oriented CPU in Verilog to build a scientific calculatorgithub.com
▲ 119gdevic 152d 💬 42
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newOpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020)github.com
▲ 87peter_d_sherman 483d 💬 9
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newao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)github.com
▲ 73csmantle 73d 💬 14
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newVectorization of Verilog Designs and its Effects on Verification and Synthesisarxiv.org
▲ 35matt_d 209d 💬 6
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newShow HN: Write, simulate and synthesize VHDL/Verilog in the browserrisingedge.pro
▲ 19wozniakpawel 83d 💬 4
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newComparing Two Verilog CPU Implementations Using EBMCwww.philipzucker.com
▲ 10todsacerdoti 610d 💬 1
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newInline-Verilog: Execute Verilog circuits from Haskellmazzo.li
▲ 10nh2 491d discuss
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newFrom Pal to Verilog: Writing the A4092 Logic from Scratchamiga.technology
▲ 7freediver 184d discuss
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newComparing Two Verilog CPU Implementations Using EBMCwww.philipzucker.com
▲ 5PaulHoule 600d discuss
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newOpensouce RISC-V CPU core implemented in Verilog from scratch in one nightgithub.com
▲ 4mococa 577d 💬 4
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newShow HN: AutoGPU – AI designs a real 7nm GPU, from Verilog to GDSIIgithub.com
▲ 4npip99 127d discuss
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newNovaGPU – An open-source GPU architecture written in Veriloggithub.com
▲ 4novastudios-hw 139d discuss
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newVerijit – Up to 100x faster Verilog simulation [video]www.youtube.com
▲ 4can_lehmann 180d discuss
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newI'll see your 372 lines of Verilog and raise you five lines of math.jamesevery.org
▲ 3JamesEvery 516d 💬 1
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newTPU: Tensor-Processing-Unit – Open-Source Verilog TPUgithub.com
▲ 3peter_d_sherman 66d discuss
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newGiulioz: MMO-CHIP: From Microscope to Verilog in an hour [video]www.youtube.com
▲ 3rasz 128d discuss
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newBuilding an Open-Source Verilog Simulator with AI: 580K Lines in 43 Daysnormalcomputing.com
▲ 3matt_d 226d discuss
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newCVDP: LLM Benchmark for Verilog RTL Design and Verificationarxiv.org
▲ 3matt_d 480d discuss
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newContrasting Verilog and SeqiLog Port List Customizationcjdrake.substack.com
▲ 3cjdrake 675d discuss
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newShow HN: FPGA-SIM – interactive virtual boards to help teach Veriloggithub.com
▲ 2theharmonic 98d 💬 1
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newA permissively licensed Vita FPGA Architecture in only 380 lines of Veriloggithub.com
▲ 2VitaSetLLC 146d 💬 1
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newBuilding an Open-Source Verilog Simulator with AInormalcomputing.com
▲ 2krupan 224d 💬 1
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newHBC (2016): Hand-Written Verilog for Offloading Column-Oriented DBs to the NICnote.com
▲ 2victrious 234d 💬 1
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newVerifrog – a Verilog/SystemVerilog testing framework an AI agent can drivegithub.com
▲ 2bryancostanich 64d discuss
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newTiny-GPU – A minimal open-source GPU design in Verilog to learn how GPUs workgithub.com
▲ 2peter_d_sherman 66d discuss
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newShow HN: FPGA design acceleration – idiomatic Python to synthesizable Verilogholoso.digital
▲ 2spym_109d discuss
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newBuilding an Open-Source Verilog Simulator with AI: 580K Lines in 43 Daysnormalcomputing.com
▲ 2hasheddan 135d discuss
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newNew PyXHDL Release (Python Frontend To VHDL And Verilog)github.com
▲ 2dadaz 161d discuss
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newPyXHDL – Python Front End for VHDL and Veriloggithub.com
▲ 2dadaz 182d discuss