Hackernews posts about Verilog

Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.

1. Less Slow C++ (github.com)
   198 points by ashvardanian 8 days ago | 97 comments
2. Show HN: Less Slow C++ (github.com)
   6 points by ashvardanian 26 days ago | discuss
3. A free and open source software, hardware and firmware PC with a eFPGA
   4 points by vitalmixofntrnt 25 days ago | 1 comments
4. How Virologists Lost the Gain-of-Function Debate (www.thenewatlantis.com)
   6 points by SCEtoAux 8 days ago | discuss
5. Thanks to Trump, your next phone from AT&T and Verizon could cost more (www.neowin.net)
   5 points by bundie 2 days ago | discuss
6. Scaling Verilator Simulations with Kubernetes and Julia [pdf] (github.com)
   3 points by akrylov 11 days ago | 1 comments
7. AIs Are Disseminating Expert-Level Virology Skills (ai-frontiers.org)
   2 points by nopinsight 4 days ago | 1 comments
8. Hackers exploiting vulnerabilities at higher rates, reports Verizon (www.scworld.com)
   2 points by LinuxBender 2 days ago | discuss
9. Visible's new plan puts Verizon's to shame (www.theverge.com)
   2 points by sea-gold 24 days ago | discuss
10. I'm 10 years old and launching my startup on stage at SaaStock. Any advice?
    3 points by agentsrihan 4 days ago | 3 comments
11. Eiotclub Launches Rugged ESIM at ISC West 2025 for Always-On Industrial IoT
    1 points by emmanol 23 days ago | 1 comments
12. Show HN: Easy Virtual Prototyping for Complex Computer Systems with SimBricks (www.simbricks.io)
    1 points by antoine-kaufm 11 days ago | discuss
13. Show HN: Nerdlog – Fast, multi-host TUI log viewer with timeline histogram (github.com)
    132 points by dimonomid 5 days ago | 50 comments
14. Show HN: Resurrecting Infocom's Unix Z-Machine with Cosmopolitan (christopherdrum.github.io)
    157 points by ChristopherDrum 12 days ago | 50 comments
15. Tiny GPU: A minimal GPU implementation in Verilog (github.com)
    315 points by fgblanch about 1 year ago | 73 comments
16. Verilog to Routing (verilogtorouting.org)
    107 points by stefanpie over 1 year ago | 29 comments
17. Verilog HDL and its ancestors and descendants (2020) [pdf] (dl.acm.org)
    28 points by JoachimS over 1 year ago | 7 comments
18. Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
    15 points by matt_d 8 months ago | 2 comments
19. Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
    13 points by sathvikr 9 months ago | 7 comments
20. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    10 points by todsacerdoti 2 months ago | 1 comments
21. Package Manager for Verilog (github.com)
    6 points by sathvikr 9 months ago | 7 comments
22. Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
    5 points by PaulHoule 2 months ago | discuss
23. Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com)
    4 points by delduca about 1 month ago | 4 comments
24. Verilog vs. VHDL: A Comprehensive Comparison (www.wevolver.com)
    4 points by alexahn over 1 year ago | 1 comments
25. Verilog2factorio: Compile Verilog into Factorio Blueprints (github.com)
    4 points by EvgeniyZh about 1 year ago | discuss
26. Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
    3 points by cjdrake 5 months ago | discuss
27. Writing a 6502 in Verilog (www.youtube.com)
    3 points by lagrange77 about 1 year ago | discuss
28. My Six Lines of Verilog Code Turing Complete BitBitJump Is Now Under the GPLv3 (gitlab.com)
    3 points by pantantrant over 1 year ago | discuss
29. Learn FPGAs, Verilog and VHDL (nandland.com)
    3 points by teleforce over 1 year ago | discuss
30. Lattice-Boltzmann in Python, C, and Verilog (vanhunteradams.com)
    3 points by vha3 almost 2 years ago | discuss
31. Variable-size Verilog floating point implementation (github.com)
    2 points by douwedb about 1 year ago | 1 comments
32. Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
    2 points by avnd about 1 month ago | discuss
33. Improving Verilog Four State Logic (cjdrake.substack.com)
    2 points by mediisoccuspupa 4 months ago | discuss
34. VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
    2 points by teleforce 4 months ago | discuss
35. Ask HN: Are there open source flow graph based Verilog generators?
    2 points by polalavik 4 months ago | discuss
36. HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
    2 points by pera 6 months ago | discuss
37. Pip Install for Verilog (github.com)
    2 points by sathvikr 8 months ago | discuss
38. Verilog Programs Are Pure Expressions (uwplse.org)
    2 points by matt_d 9 months ago | discuss
39. Python-Based DSL for Generating Verilog Model of Synchronous Digital Circuits (arxiv.org)
    2 points by belter 10 months ago | discuss
40. Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
    2 points by coconutpalms about 1 year ago | discuss
41. The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog (dl.acm.org)
    2 points by matt_d over 1 year ago | discuss
42. Basic Cordic implementation in Rust and Verilog (github.com)
    1 points by xphos about 2 months ago | 1 comments
43. Tiny-NN: A Toy Neural Network Accelerator in System Verilog (github.com)
    1 points by hasheddan about 2 months ago | discuss
44. Formal Verification for Verilog Using Yosys (cheickdo.github.io)
    1 points by yatrios 2 months ago | discuss