Hackernews posts about Verilog
Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.
- U.S. Army Soldier Arrested in AT&T, Verizon Extortions (krebsonsecurity.com)
- Nevermind Chinese spies: US Air Force picks Verizon for 35 base network upgrades (www.theregister.com)
- More telcos confirm Salt Typhoon breaches as White House weighs in (www.theregister.com)
- Want to start a fight among virus experts? Ask about HIV's new name (www.statnews.com)
- Tiny GPU: A minimal GPU implementation in Verilog (github.com)
- Verilog to Routing (verilogtorouting.org)
- Verilog Ethernet: Work-in-Progress 100BASE-TX PHY (github.com)
- Show HN: Naja-Verilog – Structural Verilog Parser (github.com)
- Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
- Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
- Package Manager for Verilog (github.com)
- Verilog vs. VHDL: A Comprehensive Comparison (www.wevolver.com)
- Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
- Writing a 6502 in Verilog (www.youtube.com)
- Learn FPGAs, Verilog and VHDL (nandland.com)
- Lattice-Boltzmann in Python, C, and Verilog (vanhunteradams.com)
- OpenROAD: Open IC Design Sythesis from Verilog (github.com)
- Variable-size Verilog floating point implementation (github.com)
- Improving Verilog Four State Logic (cjdrake.substack.com)
- VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
- HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
- Pip Install for Verilog (github.com)
- Verilog Programs Are Pure Expressions (uwplse.org)
- Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
- A next generation Verilog-A compiler (github.com)
- Verilog – Hardware register based language for standardization (en.wikipedia.org)
- Sussing Out SystemVerilog vs. Verilog (fpgacoding.com)