Hackernews posts about Verilog
Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.
- ao486 port for MiSTer (486SX FPGA core in Verilog) (github.com)
- Ongiong Nationwide Verizon Cellular Outage (www.phonearena.com)
- Verisign Is Down (www.verisign.com)
- Verily Launching New AI Health App for Data Sharing (www.bloomberg.com)
- Verizon Chooses AST SpaceMobile to Support Space-Based Cellular Broadband (www.businesswire.com)
- Verizon's I'm a Teapot Error and Other Technology Fails (thecodist.com)
- Starlink: 50 MHz of spectrum and 15K new satellites (arstechnica.com)
- Open Letter to the Free Internet (rodolphoarruda.pro.br)
- JRR Tolkien's personal book cover designs for "The Lord of the Rings" trilogy (bookofjoe2.blogspot.com)
- Tiny GPU: A minimal GPU implementation in Verilog (github.com)
- Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
- Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- Package Manager for Verilog (github.com)
- Comparing Two Verilog CPU Implementations Using EBMC (www.philipzucker.com)
- Verilog vs. VHDL: A Comprehensive Comparison (www.wevolver.com)
- I'll see your 372 lines of Verilog and raise you five lines of math. (jamesevery.org)
- Contrasting Verilog and SeqiLog Port List Customization (cjdrake.substack.com)
- Writing a 6502 in Verilog (www.youtube.com)
- Variable-size Verilog floating point implementation (github.com)
- Show HN: From Nandgame to Verilog to FPGA (github.com)
- Show HN: Penguin-rtl – Verilog equivalence checking locally in the browser (penguin-rtl.arjunv.net)
- Improving Verilog Four State Logic (cjdrake.substack.com)
- VerilogEval: Evaluating Large Language Models LLMs for Verilog Code Generation (research.nvidia.com)
- HDLBits: Getting Started with Verilog (hdlbits.01xz.net)
- Pip Install for Verilog (github.com)
- Verilog Programs Are Pure Expressions (uwplse.org)
- Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
- Basic Cordic implementation in Rust and Verilog (github.com)