Hackernews posts about Verilog
Verilog is a hardware description language (HDL) used to design and verify digital electronic systems at the register-transfer level.
- Automated feature testing of Verilog parsers using fuzzing (johnwickerson.wordpress.com)
- Pip Install for Verilog (github.com)
- Tiny GPU: A minimal GPU implementation in Verilog (github.com)
- Verilog to Routing (verilogtorouting.org)
- Verilog Ethernet: Work-in-Progress 100BASE-TX PHY (github.com)
- Learning Verilog and FPGA (johanneshoff.com)
- Show HN: Naja-Verilog – Structural Verilog Parser (github.com)
- Verilog Copilot that pulls from pre-verified libraries [video] (www.youtube.com)
- Package Manager for Verilog (github.com)
- Verilog vs. VHDL: A Comprehensive Comparison (www.wevolver.com)
- Writing a 6502 in Verilog (www.youtube.com)
- Learn FPGAs, Verilog and VHDL (nandland.com)
- Lattice-Boltzmann in Python, C, and Verilog (vanhunteradams.com)
- OpenROAD: Open IC Design Sythesis from Verilog (github.com)
- Variable-size Verilog floating point implementation (github.com)
- Verilog Programs Are Pure Expressions (uwplse.org)
- Proportional – Integral regulator in Verilog. Implementation and verification (www.controlpaths.com)
- A next generation Verilog-A compiler (github.com)
- VerilogBoy – GameBoy on FPGA (hackaday.io)
- Numbers in Verilog (projectf.io)
- Sussing Out SystemVerilog vs. Verilog (fpgacoding.com)
- Setting Up Verible for Verilog with Neovim (danielmangum.com)
- Simulating DSP algorithms using Verilog (www.controlpaths.com)
- Show HN: Manta – A tool for FPGA Debugging and Rapid Prototyping (fischermoseley.github.io)
- Show HN: SimBricks – Modular Full-System Simulation for HW-SW Systems (simbricks.github.io)