Hackernews posts about RISC-V
RISC-V is an open-source instruction set architecture (ISA) that allows for custom and flexible processor designs, making it a highly programmable and versatile platform for various applications.
- ESP32-S31: Dual-Core RISC-V SoC with Wi-Fi 6, Bluetooth 5.4, and Advanced HMI (www.espressif.com)
- The RISE RISC-V Runners: free, native RISC-V CI on GitHub (riseproject.dev)
- What is RISC-V and why it matters to Canonical (ubuntu.com)
- Tracking down a 25% Regression on LLVM RISC-V (blog.kaving.me)
- QRV Operating System: QNX on RISC-V (r-tty.blogspot.com)
- SiFive Raises $400M to Accelerate High-Perf RISC-V Data Center Solutions (www.businesswire.com)
- Talk about Open Source Chip Development with RISC-V (www.youtube.com)
- 789 KB Linux Without MMU on RISC-V (2023) (popovicu.com)
- RISC-V is the Future – Jiachen Project (rv2036.org)
- Giving RISC-V 1024 registers for zkVMs (leonardoalt.github.io)
- Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU (blog.adafruit.com)
- Samsung's BM9K1 PCIe drive's controller is based on RISC-V delivering 11.4 GB/s (www.tomshardware.com)
- Linux Foundation: Building a RISC-V CPU Core (LFD111x) (training.linuxfoundation.org)
- Optimising a pipelined RISC-V core: from naive pipeline to near-superscalar perf (mummanajagadeesh.github.io)
- Unified RISC-V IP Access Platform (openhwgroup.github.io)
- RISC-V Linux BusyBox Single Board Notebook (tomlarkworthy.github.io)
- China builds open RISC-V chip platform with Xiangshan, Ruyi OS (www.digitimes.com)
- Tracking down a 25 percent LLVM RISC-V regression (blog.kaving.me)
- Espressif Unveils ESP32-S31 Dual-Core RISC-V SoC with Wi-Fi 6 and Bluetooth 5.4 (www.techpowerup.com)
- Show HN: ADS-B Scope – Portable ADS-B and mesh radio on a LilyGo T-Display-P4 (adsb-scope.offx1.com)
- Show HN: I've Added Gdbstub to UVM32 (github.com)
- A new RISC-V Mainboard from DeepComputing (frame.work)
- Easy RISC-V (dramforever.github.io)
- RISC-V Is Sloooow (marcin.juszkiewicz.com.pl)
- A Bendy RISC-V Processor (spectrum.ieee.org)
- A Lisp compiler to RISC-V written in Lisp (www.ulisp.com)
- A trustworthy, free (libre), Linux capable, self-hosting 64bit RISC-V computer (www.contrib.andrew.cmu.edu)
- Alibaba/T-HEAD's Xuantie C910: An open source RISC-V core (chipsandcheese.com)
- Europe bets once again on RISC-V for supercomputing (www.theregister.com)
- Hacker gains access to the RP2350 OTP secret by glitching the RISC-V cores (www.tomshardware.com)
- Rocky Linux 10 Will Support RISC-V (rockylinux.org)
- A cryptographically secure bootloader for RISC-V in Rust (www.codethink.co.uk)
- RISC-V single-board computer for less than 40 euros (www.heise.de)
- Linux Runs on Raspberry Pi RP2350's Hazard3 RISC-V Cores (2024) (www.hackster.io)
- Arch Linux RISC-V (archriscv.felixc.at)
- VPR: Nordic's First RISC-V Processor (danielmangum.com)
- How to improve the RISC-V specification (alastairreid.github.io)
- Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014) (www2.eecs.berkeley.edu)
- Condor's Cuzco RISC-V Core at Hot Chips 2025 (chipsandcheese.com)
- Senior Intel CPU architects splinter to develop RISC-V processors (www.tomshardware.com)
- LuaJIT PR: Add Support for RISC-V 64 (github.com)