Hackernews posts about RISC-V

RISC-V is an open-source instruction set architecture (ISA) that allows for custom and flexible processor designs, making it a highly programmable and versatile platform for various applications.

1. RISC-V is now officially supported by CPython (blog.python.org)
   306 points by lumpa 26 days ago | 66 comments
2. Hot Chips 2026: CUDA Targets RISC-V (chipsandcheese.com)
   98 points by rbanffy 26 days ago | 14 comments
3. RISC-V Emulator and Linux System from Scratch (github.com)
   63 points by Bluestein 12 days ago | 8 comments
4. Espressif Releases Linux BSP for ESP32-S31 RISC-V Boards (www.cnx-software.com)
   6 points by jandeboevrie 28 days ago | 1 comments
5. Arbel: Building the Impossible RISC-V CPU (www.nextsilicon.com)
   6 points by ronfriedhaber 9 days ago | discuss
6. SiFive Accelerates RISC-V Datacenter Adoption with the BigSky Development Server (www.businesswire.com)
   6 points by fork-bomber 26 days ago | discuss
7. YuzukiNeko – A Linux-Capable Allwinner F101 RISC-V SBC (www.cnx-software.com)
   5 points by fork-bomber 11 days ago | discuss
8. ISO/IEC DIS 26791-1 – The RISC-V instruction set manual (www.iso.org)
   4 points by camel-cdr 26 days ago | 3 comments
9. Training a GPT from scratch in C on a RISC-V MCU with no FPU, in 37KB of code (rvembedded.com)
   4 points by armstrongsubero 11 days ago | 2 comments
10. TinyEMU is a system emulator for the RISC-V and x86 archs (github.com)
    4 points by Bluestein 7 days ago | discuss
11. Update on RISC-V Standards and Adoption at Hot Chips 2026 (www.servethehome.com)
    4 points by lumpa 16 days ago | discuss
12. ESP32-S31 dual-core RISC-V SoC is getting official Linux support (www.cnx-software.com)
    4 points by pyprism 28 days ago | discuss
13. SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers (finance.yahoo.com)
    3 points by galaxyLogic 4 days ago | discuss
14. Canonical Evolution of Enterprise Open Source RISC-V at Hot Chips 2026 (www.servethehome.com)
    3 points by fork-bomber 10 days ago | discuss
15. Canonical Evolution of Enterprise Open Source RISC-V at Hot Chips 2026 (www.servethehome.com)
    3 points by rbanffy 11 days ago | discuss
16. SERV – The SErial RISC-V CPU Topics (github.com)
    3 points by Bluestein 17 days ago | discuss
17. ArXiv: CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace (arxiv.org)
    3 points by xlbxrt 24 days ago | discuss
18. RISC-V emulator in pure Nix (github.com)
    2 points by eisbaw 5 days ago | discuss
19. Infineon RISC-V for Automotive at Hot Chips 2026 (www.servethehome.com)
    2 points by fork-bomber 5 days ago | discuss
20. Where Will RISC-V Be in 20 Years? Poll Results (thechipletter.substack.com)
    2 points by rbanffy 13 days ago | discuss
21. Where will RISC-V be in 20 years? Poll results (thechipletter.substack.com)
    2 points by klelatti 17 days ago | discuss
22. RISC-V Interpreter from the Future (abundance.build)
    2 points by arto 18 days ago | discuss
23. Tiny-Vedas: a generic accelerator interface for RISC-V, from PyTorch op to GDS (github.com)
    1 points by marcux95 about 23 hours ago | discuss
24. RISC-V: What next after RVA23? (ubuntu.com)
    1 points by cbolton 2 days ago | discuss
25. EpicSemi Contrail AIX RISC-V Servers (www.epicsemi.com)
    1 points by xlmnxp 2 days ago | discuss
26. Rvvts – The RISC-V Vector Test Framework (V2) (github.com)
    1 points by fork-bomber 5 days ago | discuss
27. Update on RISC-V Standards and Adoption at Hot Chips 2026 – ServeTheHome (www.servethehome.com)
    1 points by rbanffy 15 days ago | discuss
28. Show HN: Cactus Needle 3: 8-29MB automation models can match DeepSeek V4 Flash (cactuscompute.com)
    213 points by HenryNdubuaku 1 day ago | 89 comments
29. Show HN: A browser IDE for m68000, Z80 assembly (and more), with graphics (asm-editor.specy.app)
    31 points by specy 11 days ago | 3 comments
30. Show HN: I made a tiny MoE/Engram viz tool (sw-ml-study.github.io)
    2 points by softwarewright 6 days ago | discuss