Hackernews posts about RISC-V
RISC-V is an open-source instruction set architecture (ISA) that allows for custom and flexible processor designs, making it a highly programmable and versatile platform for various applications.
- Alibaba Launches C930 RISC-V Chip Amid Shift from Western Tech (www.hpcwire.com)
- RISC-V Sandboxing Library (github.com)
- RISC-V and Fedora: All Aboard (fedoramagazine.org)
- China to publish policy to boost RISC-V chip use nationwide (www.reuters.com)
- Jim Keller joins ex-Intel chip designers in RISC-V startup (www.tomshardware.com)
- Alibaba launches server-grade RISC-V CPU design (www.theregister.com)
- Alibaba launches server-grade RISC-V silicon, Beijing seems set to back the ISA (www.theregister.com)
- SiFive HiFive Premier P550 RISC-V Linux Performance Review (www.phoronix.com)
- U.S. Lawmakers Want to Block China from 'American' RISC-V (2023) (www.tomshardware.com)
- Fedora Rolling Out More RISC-V Infrastructure and Ready-to-Boot Images (www.phoronix.com)
- Jim Keller joins ex-Intel chip designers in RISC-V startup (www.tomshardware.com)
- China to publish policy to boost RISC-V chip use nationwide, sources say (www.reuters.com)
- Richard Stallman on RISC-V and Free Hardware (www.youtube.com)
- RISC-V Vector Programming in C with Intrinsics (fprox.substack.com)
- RVVM: RISC-V Virtual Machine (github.com)
- Alibaba launches RISC-V-based XuanTie C930 server CPU (www.tomshardware.com)
- Nvidia Shipped One Billion RISC-V Cores in 2024 (riscv.org)
- SiFive's HiFive Premier P550: powerful RISC-V board (www.jeffgeerling.com)
- Build Box64 with Box32 for x86 Emulation on RISC-V Linux (www.jeffgeerling.com)
- Chinese gov shifts focus from x86 and Arm to RISC-V chips (www.tomshardware.com)
- Ubuntu Linux Performance Has Evolved for SiFive RISC-V over the Last 4 Years (www.phoronix.com)